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Vivek Chandrasekhar

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Run time error in Verilog AMS
Oct 08^th, 2004, 8:13pm

I got this error when i was simulating my 4 bit DAC code.
The error is
out_scaled = out_scaled + ((V(bit2) > vtrans) ? 4 : 0);: Expecting only branch or node type argument

The code is as under
`include "disciplines.vams"
`include "constants.vams"

module dac (out,bit3,bit2,bit1,bit0);
output out;
input bit3,bit2,bit1,bit0;
electrical out;
logic bit3,bit2,bit1,bit0;
parameter real vref = 1 from [0:inf);
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vtrans = 1.2;

real out_scaled; // output scaled as fraction of 16

analog begin
out_scaled = 0;
out_scaled = out_scaled + ((V(bit3) > vtrans) ? 8 : 0);
out_scaled = out_scaled + ((V(bit2) > vtrans) ? 4 : 0);
out_scaled = out_scaled + ((V(bit1) > vtrans) ? 2 : 0);
out_scaled = out_scaled + ((V(bit0) > vtrans) ? 1 : 0);
end
endmodule
I would be grateful to anyone who could point out my error.
Thanks.
Vivek

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Mighty Mouse Community Member Offline Here I come to save the day! Posts: 75 Fantasyland	Re: Run time error in Verilog AMS Reply #1 - Oct 9^th, 2004, 12:38am V() is an electrical access function. It should only be applied to electrical signals. bit2 is not electrical, it is logic. You would access the value of bit2 without the access function. So you should use ... out_scaled = out_scaled + ((bit2 > vtrans) ? 4 : 0); - MM -
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Andrew Beckett Senior Fellow Offline Life, don't talk to me about Life... Posts: 1742 Bracknell, UK	Re: Run time error in Verilog AMS Reply #2 - Oct 12^th, 2004, 1:58pm In fact, it should probably be: Code: out_scaled = out_scaled + (bit2 ? 4 : 0); No point comparing a logic signal to see if it is greater than vtrans... Regards, Andrew.
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jbdavid

Community Fellow

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Posts: 378
Silicon Valley

Re: Run time error in Verilog AMS
Reply #3 - Nov 1^st, 2004, 7:54pm

And actually
if you declared that as a 4bit wide bus, rather than 4 signals: you can make this much simpler..

module dac (output out, input [3:0] bit);
electrical out;
logic [3:0] bit;
parameter real vref = 1 from [0:inf);
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vtrans = 1.2; // not needed for d2a

real out_scaled; // output scaled as fraction of 16
integer iout = 0; // output without x or z (init to 0)
always @(bit)
if (^bit ==! 1`bx or ^bit ==! 1`bz) iout = bit;

analog begin
out_scaled = out/16.0;
V(out) = vref*transition(out_scaled, tdel, trise,tfall);
end
endmodule
---
PS I do use some of the verilog2001 enhancements..
they work in NCsim -ams..
jbd

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jbdavid
Mixed Signal Design Verification

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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: Run time error in Verilog AMS Reply #4 - Nov 1^st, 2004, 7:56pm sorry that should have been outscaled = iout/16; JBD
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