I design a DAC, using current steering architecture. The base current source cell likes the picture below.
![](http://www.edaboard.com/files-eboard/cm.jpg)
The bias voltage come from bandgap circuit. it is steady. But the VDD will have 5% to 10% fluctuation becaues of the source out of the chip. So the output current will change a lot by different VDD voltage.
How can I slove this problem? Please give me some advice. It is emergency!!
Thank you very much.