The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 3rd, 2024, 1:30pm
Pages: 1
Send Topic Print
syntax problem A <= #'B C; (Read 2262 times)
MARCE
Guest




syntax problem A <= #'B C;
Feb 23rd, 2005, 4:48am
 
Hallo everybody,
can anyone help me?
I need to know what's the meaning of the following expression

A <= #'B C;


(A,B and C are 3 different clocks)

Thanks

Marce
Back to top
 
 
  IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: syntax problem A <= #'B C;
Reply #1 - Jun 6th, 2005, 8:43am
 
This isn't really an AMS question; look in your 1364 Verilog reference.
The "<=" construct is a non-blocking assignment, but usually you see something like

Code:
A <= #10 1;
B <= #5 0;
 



With the non-blocking assignment, B gets the value 0 at time 5, rather than time 15 if a regular assignment had been used.  I've never seen a delay specified as 'B as in your example, rather than as a number.  The LRM allows a number or an identifier, not an expression like 'B.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
jbdavid
Community Fellow
*****
Offline



Posts: 378
Silicon Valley
Re: syntax problem A <= #'B C;
Reply #2 - Aug 3rd, 2006, 6:21am
 
if there is a
`define B 12 somewhere.. then
#`B would expand to
#12
B may be a clock but `B is a just a macro that could be ANYTHINg..
jbd
Back to top
 
 

jbdavid
Mixed Signal Design Verification
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.