Hi Guys:


I'm working on a 12bit 65M pipeline now. Well, the problem is when using package model (inductor & capacitor from package and bondwires), there are some power/ground reboune happened. Since 3 sets of power supplies are used for analog and digital, how to set up bypass filter for these power supplies makes me confused. I do appreciate if someone could give me some ideas.


Best

Vincent

Mr. Kundert has provided a great reference that gives a general understanding.  I recommend the following approaches to solve your problem:

Soln 1:  Avoid signal dependent reference modulation (i.e. use a constant switched-cap load on the reference)
Soln 2:  Use a very low impedance on-chip reference buffer (i.e. burn much more power than you thought when you started the design!)
Soln 3:  Use massive amounts of on-chip decoupling and try to dampen the bond-wire inductance with series resistance to the top plate of the capacitor.

For 12b performance you should have capacitor mismatch issues as well.  In testing the reference modulation can look like mismatch errors and vice versa.  Try to test at multiple clock rates to separate the two effects as mismatch is mostly a static error and reference modulation has a strong clock rate dependence.

KP

When looking for sensitivity it is sometimes just as informative to make something worse as to make it better.  By that I mean, adding a bias control knob to an amplifier and reducing its settling accuracy can highlight whether settling accuracy is currently the limiting issue.  If you can reduce the settling performance and see negligible SNDR impact then its not the amps.

Microprobing the references is another way to gather information.