Dear all,
I have modified many things compared to my last post. That is the reason i am posting a new thread.
The schematic that iam working on now is
http://www.cyd.liu.se/users/~kamva881/temp/circuit.jpgI tried to simulate it. It gives me an error saying (This is a part of my output.log file)
Quote:Simulating `raw/tb_DW01_add_cla_width8' on MYHOSTMACHINE at 4:45:30 PM, Wed Mar 2, 2005.
Notice from spectre during hierarchy flattening.
timeSweep: `stop' has the unusually large value of 100 s.
Error found by spectre during initial setup.
Waveform file
`/home/coworker/kameswar/glitches/SIMULATION/CADENCE/pwlFile5' is
empty.
spectre completes with 1 error, 0 warnings, and 1 notice.
spectre terminated prematurely due to fatal error.
But my pwlFile5 is not empty. a part of my pwlFile5 is as follows.
Quote:v_B1 B<1> 0 pwl '0*(10n)' '3'
+, '0*(10n)+.3n' '3', '1*(10n)' '3'
+, '1*(10n)+.3n' '0', '2*(10n)' '0'
+, '2*(10n)+.3n' '0', '3*(10n)' '0'
+, '3*(10n)+.3n' '3', '4*(10n)' '3'
+, '4*(10n)+.3n' '0', '5*(10n)' '0'
+, '5*(10n)+.3n' '0', '6*(10n)' '0'
+, '6*(10n)+.3n' '0', '7*(10n)' '0'
+, '7*(10n)+.3n' '0', '8*(10n)' '0' ... ...... ... ..
I do not understand where the problem is. every thing that i do depends on this small test circuit which iam developing now. Plz help me.
Thanks in advance,
kamesh.