Dear all,

Recently I got a task to design a SerDes with around 1GHz data rate.
The tranmitter got a 100MHz local clock, and the the receiver got a similar but with a slight difference local clock, say 99.99MHz.

So I have to use a CDR in my receiver to extract the clock information from the embeded 8B/10B encoded serialized 1GHZ data stream.
SO my CDR will first use the local 99.99MHz as a clock reference, and I will need a Phase Dector to track the phase information of the serialized data stream.
Since I will use a CDR with multi-phase VCO, I am not sure the number of phases of that VCO, it could be 10 or 5.

I read a lot of papers, I didn't find any suitable phase detector for a 5 phase or 10 phases. I can see some papers with full rate or half rate phase detector from Razavi.

Anyone got relevant experience? Or should I generate a 1 GHz clock and use a full rate phase detector?

Thanks in advance,
Raymond

Dear Paul,

Thank you indeed. I 'd like to  explain my system clear.

I have to build a 1GHz data rate SerDes in one chip. And I have a 100Mhz+/-100ppm local reference x'tal clock on this chip. Obviously, the 10:1 ratio is due to 8B/10B encoder on chip for DC balance.

TX structure.
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> Serializer ==> 1 Bit @1GHz

I will use a PLL to generte the evenly spaced 10 phases of 100MHz clock which will serve the clock source for the serializer.


RX structure,
RX is receiving the 8B/10B coded data stream from another similar SerDes chip with embeded clock and slightly different frequency , say, 100MHz+/- 200ppm.
Since the local clock 100MHz+/-100ppm  is different from in coming embeded clock, I will have to use a CDR to recover the clock from data with embeded clock.


1 bit @ 1GHz+/- 200ppm ==> CDR ==> 10 bit@ 100 Mhz +/- 200ppm  PLUS 10 phases 100MHz +/- 200ppm

That's why I hope to have a sub-rate phase detector, say, 5 phases for the CDR.


If we use the quadrate phase detector  for CDR, I will modify the SerDes entirely, especially at clock domain.

NEW TX structure
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> 10B/8B converter ==> 8 bit @ 125MHz==> Serializer ==> 1 Bit @1GHz

So will have to generate the 8 phases 125MHz from local reference clock.

NEW RX structure
1 bit @ 1GHz+/- 200ppm ==> CDR ==> 8 bit@ 125 Mhz +/- 200ppm  PLUS 8 phases 125MHz +/- 200ppm ==> 8B/10B converter==> 10 bit@ 100 Mhz +/- 200ppm  PLUS 1 phase 100MHz +/- 200ppm from  addtional PLL.


It seems more work to me comparing with the previous structure, that 's why I am seeking the 5 or 10  phase sub-rate phase detector

One more question, how about the frequency locking range  of normal CDR phase detector, say 1%? Or less than 1 %?

Please advise,

Thanks in deed!
Raymond

Dear Paul,

I agree with you. I am considering two types SerDes for this 1GHz  test chips now;One for the 1GHz single clock version for both serializer and deserailizer.  The other, as you suggested, it seem feasible to  design a 10-phase phase detector instead of 8 if I slightly modify the structure from Razavi's proposal, so that I can directly use the multi-phase sub rate phase detector.

In order to co-operate with the scability for future, since my SerDes will have the mission to support 3.2GHz in future, probably the multi-phase solution is more attractive to me.

I just wander, there seems almost every SerDes got 8B/10B encoder in high speed link or optical link, why there is no particular paper mentioning about the 10-phase sub rate phase detector instead of 2^n sub-rate phase detector?  Is that so easy that no value to  mention it? Or I am a little stupid to keep asking stupid question while this is quite apparent for other people. It really put me in puzzle.

Anyway thank you, it seem quite clear now for the architechiture.

By the way, regarding on the Bang-Bang type and Linear type phase detector, which one is better? I am quite confused by this as well.
It seem bang bang type got large jitter, but with inherent  retime data output. Linear type phase detector have better jitter performance while it suffer from the data-clock skew which reduce the time margin.
Even in Razavi's half rate phase detector, one  paper in  2001 adopt the linear type PD, at  year 2003, another paper  they adopt a Bang-Bang type half rate PD.
Both seems to serve same application 10Gbs CDR.

Any advise?

Best Regards,
Raymond

Luo,

It looks that you are working on 1.25G Serdes compatible with 1000Base-X and 4 channel 3.125G Serdes in the future. Is that right?

I agree with Paul. Just give up the sub-rate CDR with 5 or 10 clock phase. You could choose half-rate CDR or full-rate CDR.

As the 8b/10b encoder and decoder, it is easy to design and synopsys provide them in design ware. So it is rarely described in IEEE jounals and transactions.



Best regards,
Yawei