Dear all,

I am working on the high speed SerDes design. I got some papers which mention about using the pre-emphasis and post-equalizer to improve the eyediagram at receiver side which is attenuated by cable loss.

Altough that  makes sense to use those types of techique, I feel it is quite challenging to implement it.
a) Usually we require the one original serialized data stream and one (or more than one, depends the FIR structure) very short precised delayed serialized data stream with coefficient a to bulid FIR. I just wonder how to implement the precise delay line under PVT variation?

b) Another methodology is to delay parallel data before the serializer which let us use the low frequency clock for easy implementation. The issue of this is we have to duplicate an entire serializer only for generatiing the delayed  serialzed data stream. It is big area and power copnsumption!


Anyone got relevant rexperience would help me a lot!!

Thanks
Raymond

Ya Wei,

Very much thank your suggestion. In the high speed SerDes, up to 3Ghz, we usually use multiphase clocks for MUX(serializer)  to relieve the demand of single high frequency signal which is quite difficult to be generated.

This mean we don't have the  clock whose frequency is equal to data rate. We only have the multi-phase clocks, say, 4 clocks with 1/4 data rate frequncy.

So to generate a delayed data stream become power and area hungry as we need build a additional serailizer , or otherwise we need one bit  data timing shifer ( like a a analog type shift register).

Any good idea?

Thanks and best regards,
Raymond

But my concern is, it is quite difficult

Hi, YaWei,

Well, you should be right.
One practical problem is to generate a delayed version serilized data stream: Let us consider a practical case,

Suppose the basic serializer structure as follow
8:1 MUX + Pre-driver+ Liner driver
Data stream
dPn[7:0] @ 500MHz ==> dSn[0]@ 4GHz

The "n" of dPn[7:0] stand for this is the nth 8 bit parallel data.  dPn stand for the parallel data, dSn[0] stand for the high frequency serialized data stream.


In order to build a delayed version serialzed data, we firstly  need a parallel  data shuffle to build a new arranged parallel data.

NEW dPn[7:0] == dP(n-1)[7] + dPn[6:0]
NEW dp(n+1) [7:0]== dPn[7] + dP(n+1)[6:0]
.....

Then again we need a entire serailizer to serailize the NEW parallel data to get the delayed version data stream.



I thought the above structure require double area + double power, even more if we consider the new parallel data shuffle. Is this price too high for a only one-taped premehasis? If we need a 2 taped pre-emphasis, we need third serializer, am I right?


Look forward to your reply.

Thanks!
Raymond

David Reynolds

Very much thanks your reply. May I have a example from you as you mentioned " red-rag" paper?
I am keen to see that since I got pressure to finish my architecture soon.


Can you explain your suggestion below  a little bit more detail since I don't quite follow you.
~~~~
The issue with tx based equalization is that you have to know  ahead of time how much emphasis to add... does your application allow for this?
~~~

Thansk!
Raymond

[quote author=raymond_luo2003  link=1110801864/0#4 date=1110907777]Hi, YaWei,

Well, you should be right.
One practical problem is to generate a delayed version serilized data stream: Let us consider a practical case,

Suppose the basic serializer structure as follow
8:1 MUX + Pre-driver+ Liner driver
Data stream
dPn[7:0] @ 500MHz ==> dSn[0]@ 4GHz

The "n" of dPn[7:0] stand for this is the nth 8 bit parallel data.  dPn stand for the parallel data, dSn[0] stand for the high frequency serialized data stream.


In order to build a delayed version serialzed data, we firstly  need a parallel  data shuffle to build a new arranged parallel data.

NEW dPn[7:0] == dP(n-1)[7] + dPn[6:0]
NEW dp(n+1) [7:0]== dPn[7] + dP(n+1)[6:0]
.....

Then again we need a entire serailizer to serailize the NEW parallel data to get the delayed version data stream.



I thought the above structure require double area + double power, even more if we consider the new parallel data shuffle. Is this price too high for a only one-taped premehasis? If we need a 2 taped pre-emphasis, we need third serializer, am I right?


Look forward to your reply.

Thanks!
Raymond




[/quote]


Your need a FIR to do pre-emphasis. And you need to delay the data.

You can use half-rate clock to retime data if you have.
You can also retime data by multi-phase clock in lower speed.

You might not be recommended to do 8:1 mux directly, because that will make delay hard to be get.

There is trade off, you can not have all in the same time.