Hi,

I would like to know if the use of a clock bootstrapping circuit offers potential for increased sampling jitter in a high-speed, high-resolution S&H.

Are there significant sources of sampling jitter in the on-chip circuitry used for the bootstrapping? I am looking at the architectures described by Abo et. al (JSSC, May '99), and Kaiser and Dessouky (JSSC, Mar. '01).

I don't see any information about the jitter introduced by on-chip clock generation and clock buffering circuitry, and I assume that for the normal cases (non-boosting, non-bootstrapping), the jitter from the signal generator is dominant. Is the same true for bootstrapped clocks? Are there any special design guidelines to be followed?

Regards
Vivek