vivkr
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Hi,
I am wondering how best to simulate the nonlinearity of my 12-bit DAC. Basically, I need to consider mismatch effects in order to see the INL/DNL, but if I do this with a Monte Carlo run, then it is practically impossible, since each single run itself takes several hours and generates a lot of data.
Is there an efficient way of simulating the nonlinearity of a DAC? Would it be sufficient if I just simulate the nonlinearity around the major carry transition?
Regards Vivek
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