Ramakrishna,

   The right architecture depends on many factors. In
general, using a parallel architecture is an easy way
to increase the speed of an ADC. By operating ADCs
in parallel and offsetting the Sample and Hold times
you can increase the speed. Re-using the OTA would
allow you to double the speed at the same power.
There are probably constraints on the architecture of
the switched-capacitor stage in order to use double
sampling.

   The  design will also be limited by the usual constraints,
for example, aperature jitter. Twice as fast needs the
aperature glitter needs to be twice as small.

  Using a parallel ADC introduces some new problems,
in particular, fixed-pattern noise. Unless the ADCs are
identical, there will be mismatch between the ADCs
resulting in "noise" in the output.

                                                      Best Regards,

                                                         Sheldon

The simple view:

If matching determine the cap size of the first residue stage the OTA current is proportional to the cap size and clock. In the settling performance also the second order poles of the OTA come into playand these depend on technology and used VDSAT. So if you near the secondary poles of the OTA with your required settling time it makes sense to use a parallel architecture. If not it complicate your design. If you can calibrate the residue thresholds of the first stage you dramatic change the OTA-power/cap-size/clock-frequency relationship.

If the first residue stage is multibit you have a flash A/D. The threshold mismatches between the A/D and the D/A of the first residue only define that you need in the second residue a little bigger dynamic range than defined by the bit reduction.

The absolute mismatches of the D/A of the first residue stage could be corrected in the digital domain. Instead of composing the hole digital word of the complete pipeline converter of the individula residue results you add the residue results together. So if there is a mismatch the residue result to add has also some LSB contributions representing the true D/A level. If the first residue deliver 4bit you need 16 different residue results, or to compress the storage only the corrections.

The clue today is to extract the true D/A values from conversion statistics instead of using a calibration routine and stopping normal operation. That works in principle by assuming that the signal is uniform distributed within two ideal D/A levels. From the nonuniform distribution of individual level statistics you can recalculate the DNL of the first residue D/A.

The rest is analog standard work. Have fun!