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simulating DAC nonlinearity (Read 2765 times)

vivkr

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simulating DAC nonlinearity
Nov 08^th, 2005, 7:14am

Hi,

I am wondering how best to simulate the nonlinearity of my 12-bit DAC. Basically, I need to consider mismatch effects in order to see the INL/DNL, but if I do this with a Monte Carlo run, then it is practically impossible, since each single run itself takes several hours and generates a lot of data.

Is there an efficient way of simulating the nonlinearity of a DAC? Would it be sufficient if I just simulate the nonlinearity around the major carry transition?

Regards
Vivek

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Visjnoe

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Re: simulating DAC nonlinearity
Reply #1 - Nov 8^th, 2005, 11:52am

Hi,

a lot depends of course on your DAC architecture, but in general my suggestions are:

1. For the static non-linearity (INL/DNL), if you don't want to
take the simulation penalty imposed by Monte-Carlo,
I would resort to behavioral/macro-modeling. If you only
simulate the worste case transition, you have to make
sure it's really worst case (can you ever be sure...I'd prefer
a verification which checks all DAC input codes...)

2. For the dynamic non-lineariry: apply a sine wave near
the Nyquist frequency at the DAC input.

Hope this helps a bit

Kind Regards

Peter

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