raymond_luo2003
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Dear Paul,
I agree with you. I am considering two types SerDes for this 1GHz test chips now;One for the 1GHz single clock version for both serializer and deserailizer. The other, as you suggested, it seem feasible to design a 10-phase phase detector instead of 8 if I slightly modify the structure from Razavi's proposal, so that I can directly use the multi-phase sub rate phase detector.
In order to co-operate with the scability for future, since my SerDes will have the mission to support 3.2GHz in future, probably the multi-phase solution is more attractive to me.
I just wander, there seems almost every SerDes got 8B/10B encoder in high speed link or optical link, why there is no particular paper mentioning about the 10-phase sub rate phase detector instead of 2^n sub-rate phase detector? Is that so easy that no value to mention it? Or I am a little stupid to keep asking stupid question while this is quite apparent for other people. It really put me in puzzle.
Anyway thank you, it seem quite clear now for the architechiture.
By the way, regarding on the Bang-Bang type and Linear type phase detector, which one is better? I am quite confused by this as well. It seem bang bang type got large jitter, but with inherent retime data output. Linear type phase detector have better jitter performance while it suffer from the data-clock skew which reduce the time margin. Even in Razavi's half rate phase detector, one paper in 2001 adopt the linear type PD, at year 2003, another paper they adopt a Bang-Bang type half rate PD. Both seems to serve same application 10Gbs CDR.
Any advise?
Best Regards, Raymond
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