Hi,
   I followed Ken's paper pllnoise+jitter like a cookbook(used exactly the same verilog-a models) & estimated the timing jitter in both phase & voltage domains. Both the answers from voltage & phase domains are almost same & are showing the same trend with respect to variations in PLL loop parameters.So I  beleive that I havent messed up any calculations.

   The silicon samples were probed for Timing jitter.I found no direct relation  with simulation results & probed results when loop parameters were varied. (kvc,kdet, loop filter,divide ratio).The simulation results gave an increase in jitter by 'x' when the loop parameters were varied, but the probed results produced an increase no where close to 'x'. The variations in loop parameters were deliberately kept minimal so that I would'nt invalidate any of the verilog-a models.also I re-calibrated my verilog-a models' noise parameters with new values to reflect new regions of operations of the PLL blocks when the loop parameters were varied.(there were minor variations in PFD/CP & VCO's noise parameters)

   Have I set my expectations too high to see variations as seen in simulation? Do I have to be happy with a result that simply predicts a ceiling in noise performance
for that circuit?

Have any one found strong correlations with probed results ? If yes, do I need better behavioral code to model some effect that has not been modeled?

Thanks
Srikanta