If the Verilog-AMS or VHDL-AMS is digital (i.e. normal Verilog or VHDL) and is at Register Transfer Level (RTL), then it can be synthesized using tools like Cadence's RTL Compiler, or Synopys' Design Compiler.

I don't know of any tools to synthesize AMS language designs, except to use human designers! It's significantly harder to do. It would be possible if you restricted the synthesis to a small number of circuit types, I guess, but even then I don't know if anyone is doing this commercially yet.

Regards,

Andrew.