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1) What is your OTA architecture (i.e. op amp)? Is the input device NMOS or PMOS? It is a two stage opa with rail to rail folded cascoded input stage, both nmos and pmos are used.
>> So, your input stage consists of a parallel of NMOS >> and PMOS (right?). Is it similar to Fig 9.48 on Pg. 326 >> of Dr. Razavi's textbook?
>> If this is the architecture you are using, then yes, >> your input common-mode can go from 0 to 5V. >> Ummmm interesting choice.... >> Remember the gain BW of this OTA is probably a >> pretty strong function of input common-mode! 2) What range of input CM voltages does your OTA work under (i.e. all your input transistors and current sources are in the active range)? You can check this range by varying the input CM voltage and checking the minimum and maximum input CM voltages under which all transistors are still in active region with a DC operating point analysis. so it's from 0 to vdd
>> Okay. 3) What is your OTA's output CM voltage? almost 0v
>> Why is your output common-mode not 2.5 V? Why >> did you choose your output CM to be 0V? How can >> you get any output voltage swing if you choose your >> output common-mode to be 0V? >> Why not make the output common-mode 2.5 V? 4) What are your power supplies? vss:0v vdd:5v 5) What range of "input signal" CM voltages do you want to tolerate? 0~5v
>> One important question is, why did you choose the >> flip-around gain-of-1 S/H architecture. Typically, this >> architecture is used only if you really need LOW- >> NOISE and HIGH-SPEED. However, it has definite >> input >> common-mode voltage restrictions. So, if you can >> tolerate lower speeds and higher noise, but input >> common-mode tolerance from 0-5V is important, you >> may want to consider using an architecture like in >> Figure 12.41 page 432 of Dr. Razavi's book.
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