cdrom
New Member
Offline
Posts: 4
|
Actually, I am trying to adjust the delay of the longest or the critical path in the logic circuit. Basicly, since the process variation is not controllable in most cases, if we can make the gate delay or the interconnect delay tunable or adjustable from outside, we can use the test patterns to test and adjust the delay of the circuit, this will give us a chance to erase the effects of the process variation.
transistor sizing is a possible way to do that, but I guess it will require too much space if we want to make all the gate sizes adjustable.
I am trying to use the adjustable power distribution or tunable capacitors to do the trick, but not effective enough, actually. Any better ideas?
|