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Anyone knows how to do adjustable design (Read 4917 times)
cdrom
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Anyone knows how to do adjustable design
May 29th, 2005, 8:00pm
 
I want to design some some adjustable components for the circuit so that the speed of the whole circuit could be controlled. I knew the following design skills:

1. Adjust the power voltage.
2. Insert/Delete some capacitors on the interconnect lines.

Anyone knows other design methods? Such as change the substrate voltage of the transistor? Is this a good option since I am not sure if people can chage individual transistor's substrate voltage on the die.


Thanks in advance.
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sheldon
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Re: Anyone knows how to do adjustable design
Reply #1 - Jun 1st, 2005, 8:35pm
 
cdrom,

  More details would be useful. In the case of VCO's you might want to control
the bias current current of the  blocks or control the capacitor value(as you  
mentioned). Usually, bias current has a stronger correlation with speed than
the power supply voltage. Depending on what you are doing, you could
switch in/out different size gain transistors.

                                                                              Best Regards,

                                                                                 Sheldon
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cdrom
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Re: Anyone knows how to do adjustable design
Reply #2 - Jun 10th, 2005, 11:21am
 
Actually, I am trying to adjust the delay of the longest or the critical path in the logic circuit. Basicly, since the process variation is not controllable in most cases, if we can make the gate delay or the interconnect delay tunable or adjustable from outside, we can use the test patterns to test and adjust the delay of the circuit, this will give us a chance to erase the effects of the process variation.

transistor sizing is a possible way to do that, but I guess it will require too much space if we want to make all the gate sizes adjustable.

I am trying to use the adjustable power distribution or tunable capacitors to do the trick, but not effective enough, actually. Any better ideas?


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Andrew Beckett
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Re: Anyone knows how to do adjustable design
Reply #3 - Jun 12th, 2005, 12:19pm
 
One way I've done this in the past (in a delay locked loop) is to use a simple voltage regulator to control the supply to the inverter chain in the delay locked loop - adjusting the supply to the inverter chain such that one cycle of the incoming clock matches the whole inverter chain.

Regards,

Andrew.
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cdrom
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Re: Anyone knows how to do adjustable design
Reply #4 - Jun 14th, 2005, 5:38am
 
That is Cool!!!

Can you provide any of your publications or references so that I can look at your previous work? If you can drop a message to me, I will really appreicate your help.

Thanks.


[quote author=Andrew Beckett  link=1117422002/0#3 date=1118603976]One way I've done this in the past (in a delay locked loop) is to use a simple voltage regulator to control the supply to the inverter chain in the delay locked loop - adjusting the supply to the inverter chain such that one cycle of the incoming clock matches the whole inverter chain.

Regards,

Andrew.
[/quote]
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ywguo
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Re: Anyone knows how to do adjustable design
Reply #5 - Jun 17th, 2005, 11:45pm
 
Hi, Adrew and CDROM,

Put all transistor on the critical path in isolated Nwell and Pwell.  Adjust the bulk voltage, then the threshold voltage must vary due to substrate-bias. The delay will decrease if the threshold voltage decreases, and increase if the threshold voltage increases.

The above method was used in low power design. I think it is also meet your requirement.

The delay of the CMOS logic circuit increases if the supply voltage scaling down. So it is diffcult for you to reduce the delay along the critical path if you use a voltage regulator like that in a common VCO or DLL.


Best regards,
Yawei
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Andrew Beckett
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Re: Anyone knows how to do adjustable design
Reply #6 - Jun 20th, 2005, 3:13am
 
I'd also suggested (in an off-line message) that CDROM just did some searching on google to find a number of papers on such things.

Regards,

Andrew.
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