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raymond_luo2003

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Is Assura good enough for 0.13um CMOS verification
Jun 16^th, 2005, 3:01am

Dear all,

It seems many mixed-signal design teams select Calibre for 0.18um/0.13um Physical verification. Calibre look like a golden tool.

Unfortunately, my situation is a bit different. Our boss want to buy all the mixed-signal EDA tool from Cadence, the question become is the Assura good enough for the Physical verification? Do those foundry ( TSMC, UMC, Chartered) support the Assura for their 0.13um/0.18um process?

And how about Hercules from Synopysis, is this tool good enough for Physical verification for 0.13um/0.18um CMOS?

Anyone can help me understand this is very much appreciated!!
Thanks in advance!!

Raymond

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Andrew Beckett

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Re: Is Assura good enough for 0.13um CMOS verifica
Reply #1 - Jun 16^th, 2005, 4:53am

Of course, Assura is a perfectly good tool for 0.13um, 90nm etc physical verification. I don't know much about UMC, but both TSMC and Chartered have Assura rules for their processes.

Regards,

Andrew (you may consider me biased considering my employer, but this was intended as an honest answer to your question...)

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raymond_luo2003

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Re: Is Assura good enough for 0.13um CMOS verifica
Reply #2 - Jun 16^th, 2005, 5:23am

Dear Andrew,

Thanks your honest answer!

One of my feriend told about following

"Most of the foundries ( for instance , TSMC) using Calibre for final DRC check. If we use assura, most likely the first gds submitted to the foundry will be rejected because assura cannot detect 100% drc errors. We will have to fix some bugs."

Is this correct? Or this is possible due to the incomplete rule deck ( or rule techonology file) for Assura DRC/LVS?

And how about Assura xRC, is it good enough to extract parasitic RC for multi GHz circuit design?

Thank you anyway!
Raymond

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asdf

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Re: Is Assura good enough for 0.13um CMOS verifica
Reply #3 - Jun 16^th, 2005, 7:01am

Do those foundry ( TSMC, UMC, Chartered) support the Assura for their 0.13um/0.18um process?

Mentioned foundrys provide Cadence PDKs (Process Design Kit) and for example TSMC provides PDKs for 90nm, 0.13um, 0.18um and other processes.
Note that PDKs contain Assura dacks (for DRC, LVS & RCX)

Best regards

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Paul

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Re: Is Assura good enough for 0.13um CMOS verifica
Reply #4 - Jun 19^th, 2005, 1:53pm

Raymond,

I believe Calibre and Assura are both very good tools and I can certify that UMC too delivers Assura rule files for their technologies. If one tool does not find errors found by the other, you shall not blame the tool! It means that the rule files written for both tools are not the same and that's a design kit issue, not a tool issue. As far as I know, many foundries indeed use Calibre for DRC verification, but it's their job to make the Assura rules correspond, such that you get the same DRC result when using Assura. This is mostly, but not always the case, so that you may have to play with the rule deck in some cases (this may even be true if you use Calibre...).

Regarding extraction, Assura xRC is superior to Calibre with respect to inductance extraction. For RC extraction, I guess they are comparable, but Assura back-annotation into a Cadence flow may be easier.

Hope this helps

Paul

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