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ericjohnson

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Inputs DC bias for the fully dif sampler?
Jun 21^st, 2005, 10:27pm

Hello,
I was thinking and running some simulation of the BPS fully differential sampler, and got a little confused about the biasing of the fully dif amplifer. For examples, in Baker or Razavi's book, the 2 outputs are connected to the 2 inputs thru two switches (which are supposed to turn off first). But How is the DC biasing point set?

thanks,

Eric

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Inputs DC bias for the fully dif sampler? Reply #1 - Jun 22^nd, 2005, 10:32pm Eric, Rare textbooks give description about DC biasing for fully differential amplifier. Of course the DC input should be biased at a desired voltage. But please give more details about the circuit in Baker or Razavi's books if you need detailed help. Best regards, Yawei
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ericjohnson

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Re: Inputs DC bias for the fully dif sampler?
Reply #2 - Jun 22^nd, 2005, 11:07pm

Yawei,
I guess we couldn't upload the schematic to this forum. So I assume you and many others all have Baker's book. It's on page 725, figure 27.9. If not, you can check out the schematic here: http://cmosedu.com/cmos1/figs/Figs_27.pdf

This should be a 2-input, 2-output fully diff amp. When Phi1 is high (sampling period), the inputs and outputs are connected together. Suppose this is a 2-stage folded cascode amp with single power supply 2.5V and CM voltage at 1.25V.

For the case of single ended amp, we can configure it as follower with positive input connected to Vcm. Then both inputs would be set at Vcm (assuming no offset). But for this fully differential version, I couldn't see how the inputs are biased. Did I miss something here?

Thank you!

eric

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Inputs DC bias for the fully dif sampler? Reply #3 - Jun 22^nd, 2005, 11:39pm Eric, Please refer to a paper by Stephen H. Lewis, "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," JSSC 1987. (Figure 6) The differential inputs of the OPAMP should be tied to a DC bias point at sampling phase. I hope that would be helpful. Best regards, Yawei
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ericjohnson

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Re: Inputs DC bias for the fully dif sampler?
Reply #4 - Jun 23^rd, 2005, 7:46am

Yawei,

I haven't read that paper but I did test the configuration as you described. In my setup, I have another two MOS switches connecting the two inputs to Vcm. The two switches are controled by the same clock Phi1. I wan't sure about this since this actually connects the outputs to Vcm directly during sampling period. Did I do it correcly? Any other comments?

Also, how much delay should I have between Phi1 and Phi2 clock falling edges, and Phi2 falling edge and Phi3 rising edge? Say for a 100MSPS?

Thank you very mcuh,

Eric

p.s.: I just checked the paper, but it's a different topology which I can understand. Could you take a look at the configuration I described and provide some insights? Thanks!

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ywguo

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Re: Inputs DC bias for the fully dif sampler?
Reply #5 - Jun 29^th, 2005, 10:09pm

Eric,

I was busy in the past days. Sorry to reply late.

Since I havn't Baker's book, I only have a guess. The circuit looks like a flip-around sample and hold. The common mode input is set to Vcmo, common mode output voltage, at phi 1, instead of an independent common mode input voltage.

I have no idea that the delay from falling edge of phi 1 and the falling edge of phi 2. About the delay from the falling edge of phi 2 to the rising edge of phi 3, it seems to be a non-overlapping time. That means 0.5ns ~ 1ns is enough.

I hope it would be helpful.

Best regards,
Yawei

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