neoflash
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Mixed-Signal Designer
Posts: 397
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[quote author=Kart_Mann link=1119890833/0#0 date=1119890833]Hi, I'm reading up on charge pump PLLs for a project I'm working on. I am unable to understand what could limit the lock range of a Charge Pump PLL. I cannot think of any limiting factor other than maybe the volatge swing limit of the charge pump, Yet when I try to simulate such a PLL ( in Verilog AMS ) I find that there is no lock outside the range 950-1050 khz. 1Mhz being the central frequency.. Is it a fault with my simulation or with my understanding?? Specifically i'm interested in circuits using the phase detector as described by Alexander JDH in his paper on Clock recovery in Random Binary Signals Electronics letters 1975 kartik [/quote]
In theory, there is not anything limit PFD's acquisition range.
However, the lock range, which is called hold range normally, should have no definition on PFD.
In PD, lock range means that static phase error in PD should be lease than some value to keep PD gain in monotony. This is not a problem in early-late PFD.
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