Hi Kartik,

I dont have the Razavi book with me and so I cannot comment on the Alexander paper. However, I suspect that you are using only a phase detector and not a PFD (phase frequency detector) and perhaps you are referring to the acquisition range when you use the term lock range.

I dont know what scheme you are using to test for PLL locking. The standard test would be to supply an input reference clock and try to get the VCO frequency to lock to this frequency (or a multiple of it). Since you are modelling all these blocks in Verilog, the usual restrictions such as limited frequency range of the VCO etc. do not come into play.

One point to keep in mind is that the bandwidth of the loop filter also has a role to play in the whole scheme of things and if this has a sufficiently low bandwidth and you dont use a PFD, you are unlikely to get any sort of acquisition. Try using a PFD. It is very simple and described in sufficient detail in the very first paper which is a tutorial by Razavi.

To summarize, charge-pump PLLs with PFDs do not really have limitations on their acquisition behavior and you should see this if you simulate everything correctly. In addition, if your loop is stable, then the PLL stays locked once acquisition is complete.

Hope this helps.

Vivek

Hi Kartik,

I assumed that you already had the text in question since you quoted an obscure paper to begin with. Anyway, the book is titled "Monolithic Phase Locked Loops and Clock Recovery Circuits". The author is Behzad Razavi and the publisher is IEEE Press. The paper in question is the first one in the book which is actually a tutorial.

If you dont have this book, you can find more or less all the information in the textbook by Razavi "Design of Analog CMOS Integrated Circuits" in Chapter 15 which deals with PLLs.

Both Type I (XOR) and Type II (Gilbert multiplier) phase detectors have some restrictions. For more information, you can refer to the book above. Unless you have some special reason to use the Type II phase detector (which is quite fine otherwise), I would suggest using a PFD as it simplifies things quite a bit. However, that is a different matter altogether.

Regards
Vivek

[quote author=Kart_Mann  link=1119890833/0#0 date=1119890833]Hi,
I'm reading up on charge pump PLLs for a project I'm working on.
I am unable to understand what could limit the lock range of a Charge Pump PLL.
I cannot think of any limiting factor other than maybe the volatge swing limit of the charge pump,
Yet when I try to simulate such a PLL ( in Verilog AMS ) I find that there is no lock outside the range 950-1050 khz. 1Mhz being the central frequency..
Is it a fault with my simulation or with my understanding??
Specifically i'm interested in circuits using the phase detector as described by Alexander JDH in his paper on
Clock recovery in Random Binary Signals
Electronics letters 1975
kartik [/quote]

In theory, there is not anything limit PFD's acquisition range.

However, the lock range, which is called hold range normally, should have no definition on PFD.

In PD, lock range means that static phase error in PD should be lease than some value to keep PD gain in monotony. This is not a problem in early-late PFD.