James
Community Member
Offline
snowfiled
Posts: 32
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Dear Ken,
Thanks for your answer which helped me a lot in VCO simulation. Now I am simulating another block's pnoise, a 3 stage ripple counter.
The input frequency is 200M, the output is 25M. In the PSS setup form, I set beat frequency as 25M.
I have a few questions on Pnoise setup: 1. For the "Input Source", which option I should choose. I choose voltage and tried to select the wire of the input signale, but it give me the "object selected is not a valid selection object" message. Then I changed to current, port, but it gave me the same msg.
Should I choose input source as "none" ? But in your pnoise+jitter, it says, for divider, the input noise dominant. So I don't think it's should be set to none. But in my simulation, I set it to none since I couldn't set it to other values.
2. In pnoise setup form, I choose Noise Type as jitter. I think it will directly give me the ripple counter output jitter. Since the PFD is the next stage after the counter, I set the cross direction as "rise" and Threshold Value as 0.63V. I choose 0.63V because the nmos threshold voltage is 0.63V. I am not sure if I am correct on setting this value.
3. After simulation, I try to watch the result. In the pnoise jitter result option, there are "cycle to cycle", "long term", "edge to edge" options. Which one we usually use for jitter calculation?
4. I choose "cycle to cycle", and integrte range is from 1 to f0/2, f0 is the beat frequency. That is from 1 to 12.5MHz. But the result is rather small: 67fs. I changed to "long term" and "edge to edge", althouge the results are difterent, they are still in fs range. I wonder this result comes from my possibly wrong "threshould value", after I reset it to 2.5V (the supply if 5V), I got jitter 71fs. At this point, I suspect it's the reason I set "Input source" as none, but I am not sure. Your help will be highly appreciated.
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