How do I write simulation results to a file?

I've followed your advice, but it doesn't work.

The following code

       @(timer(1p,deltaT)) begin
         $fstrobe(fptr,"%g %g",reff1, reff2);
       end

leads to the following error message:

'src/cswb_4_file.vla', line 108: Error : Illegal identifier specified. Identifiers starting with '$' must identify system tasks or functions.
'src/cswb_4_file.vla', line 108: Error : 'fstrobe' must be a variable.
'src/cswb_4_file.vla', line 108: Error : Syntax error
'src/cswb_4_file.vla', line 108: Error : Syntax error near '('.

Thanks in advance.

The $f-functions are defined in the IEEE 1364 Verilog Language Reference Manual, from which the Verilog-AMS LRM is derived.

Apparently, the AMS $fopen/$fclose system tasks are slightly different, and hence are defined for AMS in the AMS LRM, but the tasks to do anything with the opened file are identical to the 1364 definitions, and thus are omitted.  I think that makes it hard to use the AMS LRM, but fixing that wasn't in the project scope when I updated the LRM to 2.2.

1364-1995 Verilog has $fstrobe $fdisplay $fwrite as well as a few special versions of these for binary data.  I'm surprised that any simulator would not have these, since they've been in the language for years.  (The 1995 version had only limited provision for *reading* from a file.)

BTW, the full 2.2 AMS LRM is available from
http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.2/AMS-LRM-2-2.pdf

-Geoffrey

Thanks Geoffrey - I was sure this was part of the language (should have remembered that it's standard Verilog), but didn't have time yesterday to look it up properly.

Andrew.

Eldo supports both.

If you are including a Verilog-AMS file in an eldo testbench, you have to use
vasim testbench
instead of
eldo testbench

Just to clarify based on MY observations with one vendors tool - the way you open, close and write to files is a little different if you do it in the analog or digital domains..  - Pay close attention to IEEE-1364 when working in an "always" or "initial" block, and
closer attention to the Verilog-AMS LRM when working in an analog block.. or when writing Verilog-A models .. At least for now.
Jonathan

[quote author=Geoffrey_Coram  link=1121755337/0#4 date=1121859017]The $f-functions are defined in the IEEE 1364 Verilog Language Reference Manual, from which the Verilog-AMS LRM is derived.

Apparently, the AMS $fopen/$fclose system tasks are slightly different, and hence are defined for AMS in the AMS LRM, but the tasks to do anything with the opened file are identical to the 1364 definitions, and thus are omitted. -Geoffrey [/quote]