Hi, All

I have a question about the spec of a ADC

"Sampling rate of 48Ms/s
SFDR>57dB @ 36MHz input frequency
3rd order intermoduation>57dBc (2 tone 35MHz and 37MHz)
"
Because the sampling frequency is 48MHz, so the bandwidth should be less then 24MHz, then why they test the SFDR outside the bandwidth? Thanks a lot!

Another way to look at it is this. Sampling can also be used as downconversion. If the input is a narrowband signal, then sampling at a lower rate effectively downconverts the signal while retaining the information content. If the input sample-and-hold is able to perform this task while ensuring good level of accuracy, then the signal may be digitized directly in this fashion. I believe the term "subsampling converter" is used to denote a data converter operating in this manner.

However, the sampling and input frequencies must be such that there is no aliasing (I think that is the only condition), and the sampling jitter does not lead to excessive noise (since this is dependent on the input frequency).

I dont think the specs imply that a wideband signal of upto 36 MHz is being used.

Vivek