Hi,

I would be grateful if someone could suggest a good way of accounting for excess thermal noise in CMOS transistors when the channel length is small. I know that there is an increase in measured noise which is largely dependent on the process and strangely enough, this is never included in the models despite this. Various theories abound on the net where some people suggest that the noise power is 3-4 times higher for L < 1um. Others say that noise voltage is higher by the same amount etc. A recent JSSC paper says that the excess noise is very small in opposition to all these theories (JSSC, Mar. 2005, Han et. al, "Complete High-Frequency Thermal Noise Modelling ....)

I am working with a 0.8um process and trying to design a very high-performance, low-noise opamp. Hence I am faced with the dilemma of using min. length input transistors or not.

Any hints?

Thanks
Vivek