Hi,

I have a lumped model consisting of ideal L, R & C elements to represent a microstrip transmission line in my Cadence schematic and I am trying to make this LVS (using Calibre LVS) with a strip of top-layer metal (over a ground plane) in my Cadence Virtuoso layout.  

I understand that that there is some sort of cookie-cutter method whereby I can have the schematic and layout match up by name if there are the same number of terminals even though the internals don't match up.

Any help with my problem is greatly appreciated.

Cheers
Jim

Hi Paul,

Thanks for the reply.  The problem is that I know that you can do some sort of black box thing, but I don't actually know how to do this with Calibre.  Could you point me in the direction of a soloution or some documentation.

Cheers

Hi Paul,

That's it! I really appreciate your help.

Cheers
James

Right Jim,

I forgot that "detail". Maybe there is a solution through LVS statements I do not realize right now, but I believe you need to add a marker layer to separate both pins of your microstrip line. Add a marker layer to your layout layers and put it as a rectangle overlapping the metal wire between both pins.

Then you need to add a component rule to your LVS rules, you can use the one typically used for resistors (they are drawn this way). Extract a resistor of any value, as it appears in the black box, it will not be compared. Check the DEVICE statement in the SVRF manual, it should be something like:

DEVICE R (R_fake) RDUM METx METx (POS NEG)

where Rfake is a fake model name, RDUM is the layer name you obtained from layer derivation (RDUM = METx AND MARK_LAY)

Nothing needs to be changed in the schematic view, as the box is already OK.

Paul