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Hi Ken and other friends, I read Ken's paper-Predicting the phase noise and jitter of PLL-based frequency synthesizers, and I am puzzled about the following issues, would you please give any hints?
#1. When making the Verilog-A model with accumulating jitter, dT always equals jitter*Gaussian_distribution. However, the jitter expressions are different in LISTING11~14: $LISTING11: jitter equals period jitter. $LISTING12: jitter equals sqrt(K)*period_jitter, what is the mean of K here? If K means k cycles, why select k-cycle jitter? $LISTING13: jitter equals sqrt(K)*period_jitter,too. But K=4 in this case. $LISTING14: jitter equals sqrt(ratio/2)*period_jitter, what is the mean of ratio here?
#2. When making the Verilog-A model with synchronous jitter, dt always equals edge-to-edge jitter*Gaussian_distribution in LISTING9~10, we select edge-to-edge jitter not period jitter, cycle-to-cycle jitter or k-cycle jitter. Why?
#3. The edge-to-edge jitter expression, formula (55) on page28, equals the period jitter expression in table2 on page26. Does this mean that the edge-to-edge jitter is the same with period jitter in synchronous jitter type blocks such as PFD/CP and FDs?
#4. What is the edge-to-edge jitter expression in accumulating jitter type blocks?
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