Hi Ken and other friends,
I read Ken's paper-Predicting the phase noise and jitter of PLL-based frequency synthesizers, and I am puzzled about the following issues, would you please give any hints?

#1. When making the Verilog-A model with accumulating jitter, dT always equals jitter*Gaussian_distribution. However, the jitter expressions are different in LISTING11~14:
$LISTING11: jitter equals period jitter.
$LISTING12: jitter equals sqrt(K)*period_jitter, what is the mean of K here? If K means k cycles, why select k-cycle jitter?
$LISTING13: jitter equals sqrt(K)*period_jitter,too. But K=4 in this case.
$LISTING14: jitter equals sqrt(ratio/2)*period_jitter, what is the mean of ratio here?

#2. When making the Verilog-A model with synchronous jitter, dt always equals edge-to-edge jitter*Gaussian_distribution in LISTING9~10, we select edge-to-edge jitter not period jitter, cycle-to-cycle jitter or k-cycle jitter. Why?

#3. The edge-to-edge jitter expression, formula (55) on page28, equals the period jitter expression in table2 on page26. Does this mean that the edge-to-edge jitter is the same with period jitter in synchronous jitter type blocks such as PFD/CP and FDs?

#4. What is the edge-to-edge jitter expression in accumulating jitter type blocks?

Hi Ken,
Thank you very much for your reply. I have two questions again:

#1. Is the period jitter’s expression the same for accumulating jitter and synchronous jitter? Always be (ct)^1/2?

#2. My simulation using EldoRF simulator (I have no SpectreRF’s license) shows that adding some small capacitors (~10fF) on the circuit nodes will help the nonlinear circuit such as PFD be convergent when doing steady-state simulation. If I remove these capacitors, it will not be convergent. What are your opinions on the role of such small capacitors? Is there similar phenomenon in SpectreRF when doing PSS simulation?

Thank you sincerely.

Hi Ken,
Thank you for your patient respondence again.

Still about the case: #1 (i.e., several jitter forms in driven circuits)
#1.1 We can get the edge-to-edge jitter J_ee with strobe noise capability of SpectreRF that is illustrated on page28 in your paper. According to formula (50) on page27, then we can get k-cycle jitter J_k, furthermore, formula (51) and (52) shows that cycle-to-cycle jitter J_cc equals J_k so that we can get J_cc. Is it right?

#1.2 In the formula (51) and (52), does the J means period jitter? (In section 10, J means period jitter) If yes, does it mean period jitter in driven circuits equals sqrt(2)*J_ee? If no, what is the period jitter expression in driven circuits? Or the period in driven circuits is meaningless?

#1.3 In my opinion, the definition of period jitter is valid for both accumulating jitter and synchronous jitter, but can not distinguish these two jitters. So why not define the constant c in driven circuits?

Thank you!