Because RC(X) components are also extracted between parallel connected schematic devices there is no good reason to parallel combine schematic devices.

The problem is that RC reduction of an extracted netlist should follow a specfic rule. Today this rule is either to specify a global minimum cap or res or to select a subset of nets. Only the circuit simulation could tell the RC netlist compressor which parasitic have which effect. That depend also on the different simulation cases normally applied in a series of verification steps. So a complete different approach is needed to overcome the stupid extraction down to some mOhm and aF. Not to speak about of the inductive coupling effects.

I am interested in a more engineering approach for extraction and verification and know these issues for about 5 years hitting the machine limitations which a 100k analog design. But up now I did not notice any new concept either.