Paul
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Raymond,
considering jitter tolerance (tracking of input jitter) only, it is exactly the opposite. Having the first clock edge in the center of the jitter distribution is good, but in presence of large high-frequency jitter it is even better if this edge moves around with the jitter. For best performance, you would like to track a maximum possible of high-frequency jitter to have the sampling in the middle of the eye even in presence of high-frequency components.
As a side note, unless you are using a half-rate scheme, you should avoid calling this Clock_I and Clock_Q, this increases the confusion. In a full-rate CDR, they are rising and falling edges of the same clock signal and not quadrature signals.
If you design SONET compliant CDRs, you must be aware that jitter tolerance is not the only spec. Jitter generation and jitter transfer impose other constraints on the PLL corner frequency, so that you cannot simply design for the highest possible PLL bandwidth.
Paul
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