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raymond_luo2003

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CDR when eye open with only 0.5UI
Oct 25^th, 2005, 4:35am

Dear all,

I really wonder the eye diagram definition in most serial link standard such as SATA, 1394 and USB2.0. I understand the eye closure is decided by deterministic jitter and random jitter which are above jitter corner frequency. Also I understand those high frequency jitter is not tracked by CDR at receiver side if CDR have low pass filter with same jitter corner frequency.

Usually jitter corner frequency is defined as fc/1667 or fc/2500 while real DJ frequency (from data dependant jitter, duty cycle jitter, supply noise jitter) are much high than jitter corner frequency.

In some of circumstance, the eye opening at receiver side is only 0.5UI. When we implement the clock data recovery circuitry to recover the data from such eye, usually we have two clocks, CLK_I (align to data transition edge) and CLK_Q (sample the data at middle point of data period) with 0.5UI distance.

Since the 0.5UI (DJ and RJ) is not recovered by CDR, I just wonder how can CLK_Q can sample the correct data with no margin [UI- 0.5UI (distance between CLK_I and CLK_Q) - 0.5UI (DJ+RJ) ==0) even the CDR have no internal generated jitter?

At some extreme case, the DJ+RJ=0.6UI, that means eye-opening is only 0.4UI left. Do we have to use over-sampling style CDR to recover the data?

Does this mean the DJ is partially traceable by CDR?? Anyone can help me to understand this???

Many thanks!

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Paul

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Re: CDR when eye open with only 0.5UI
Reply #1 - Oct 25^th, 2005, 1:28pm

Hi Raymond,

I guess there is a slight misunderstanding... If your CDR works correctly, an eye opening of 0.5UI (respectively 0.4UI) equals a margin around the sampling point of 0.25UI (respectively 0.2UI).

Consider a total jitter of 0.6UI. In average, as jitter is a statistical phenomenon, your data edge will be located in the middle of the jitter distribution (under the assumption it is symmetrical). Consider this time instant as t=0UI. Your sampling instant (what you call CK_Q) will the be located at t=0.5UI, while the jitter distribution on the initial data edge spans 0.3UI to each side (from t=-0.3UI to t=0.3UI). The same applies to the second data edge, where total jitter spans from t=0.7UI to t=1.3UI. You see that there is a margin on the sampling instant of 0.2UI on each side, the total being the eye opening of 0.4UI.

Have a look at Maxim's AppNotes on jitter in communication systems:
http://www.maxim-ic.com/appnotes.cfm/appnote_number/794
http://www.maxim-ic.com/appnotes10.cfm/ac_pk/11#49

Hope this helps

Paul

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raymond_luo2003

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Re: CDR when eye open with only 0.5UI
Reply #2 - Oct 31^st, 2005, 6:11am

Dear Paul,

Very much thank your reply which really help me understand the points. One more question, does that mean we need design CDR loop bandwidth as low as possible (as long as it is above jitter corner frequency) to filter all high frequency jitter to keep CLK_I(transition sample point) at center of jitter distribution?

If CDR loop bandwidth (Fbw) is much high than jitter corner frequency(Fjc), the CDR would try track those jitter which is between Fbw and Fjc. An extreme case ( not realistic ) if Fbw is infinite, the CDR will keep tracing all jitter while there is totally no magin for the CLK_Q(data sampling point) since 0.5UI will be greater than the eye opening -say 0.4 UI.

Thanks again!!
Raymond

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Paul

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Re: CDR when eye open with only 0.5UI
Reply #3 - Nov 1^st, 2005, 12:02pm

Raymond,

considering jitter tolerance (tracking of input jitter) only, it is exactly the opposite. Having the first clock edge in the center of the jitter distribution is good, but in presence of large high-frequency jitter it is even better if this edge moves around with the jitter. For best performance, you would like to track a maximum possible of high-frequency jitter to have the sampling in the middle of the eye even in presence of high-frequency components.

As a side note, unless you are using a half-rate scheme, you should avoid calling this Clock_I and Clock_Q, this increases the confusion. In a full-rate CDR, they are rising and falling edges of the same clock signal and not quadrature signals.

If you design SONET compliant CDRs, you must be aware that jitter tolerance is not the only spec. Jitter generation and jitter transfer impose other constraints on the PLL corner frequency, so that you cannot simply design for the highest possible PLL bandwidth.

Paul

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