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The Designer's Guide Community Forum › Modeling › Behavioral Models › time step in spectre sim using verilogA models
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time step in spectre sim using verilogA models (Read 3172 times)
parthsv
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time step in spectre sim using verilogA models
Nov 04th, 2005, 4:05pm  
Hi All,
 I am using verilogA model of pipeline with circuit model of digital calibration to test the calibration algorithm. When I run spectre I find that the spectre uses 1p r so as timestep., which results in long simulation time. Is there away to specify timestep?

Thanks in Advance.

Regards,
Partha
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Ken Kundert
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Re: time step in spectre sim using verilogA models
Reply #1 - Nov 4th, 2005, 11:06pm  
You can use the maxstep parameter to make the timestep smaller, but you cannot make it larger other than by loosening tolerances, which may not help in this case. You should first try to determine why the timestep is small.

-Ken
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