Hi all,

Could you help me, I have a problem following:
I utilise the simulator ADVance MS v3.0_1.1 to simulate all circuits in Vhdl-ams. It's ok.

Now I want to integrate a module written in Verilog in the program (code) of Vhld-ams, so I have to compile the module in Verilog before. When compiling this Verilog module, the command is:
valog source/Verilog/res.va -ms (compile file res.va – very simple resistor - with the option “-ms” – obligation). But I encounte the error as following:

# Compiling file source/Verilog/res.va
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 11 2003
# ** Error: (vlog-25) Invalid ModelSim library "/tima3/dang/VHDL-AMS/work". No _info file found.
# No such file or directory. (errno = ENOENT)
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(1): Cannot open `include file "constants.h"
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(2): Cannot open `include file "disciplines.h"
# -- Compiling module res
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(7): near ",":  expecting: '('
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(8): near "exclude":  expecting: ',' ';'
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(11): near "<":  expecting: ',' ';'
# ** Error: /tima3/dang/VHDL-AMS/source/Verilog/res.va(11): near "/":  expecting: ',' ';'

Could you tell me what to do, how to correct these errors? If I use the command:
valog source/Verilog/res.va (without option -ms)
there is no error, but I cannot call (instantiate) this Verilog module in the vhdl-ams program (par ex. in the file testbench).

Thanks you very much.

PS: code of res.va
`include "constants.h"  
`include "disciplines.h"
module res(p, n);
inout p, n;
electrical p, n;
parameter real r=1 exclude 0;
analog begin
   I(p,n) <+ V(p,n)/r;
end
endmodule