Hi,
I am trying to simulate a symmetric VCO, (Maneatis load).If I am supposed to start the design for a given frequency of operation, I would decide my number of stages and hence the delay of 1 stage. AS per the paper it is the use of variable resistance and not the  Ceff that provides the variation in frequency. My question is how do I assume my Ceff at the first design entry for a 0.6um process.
Another doubt is whether the Ceff value will change with variation in my W values.
Thanks,
V