Hi,

I've been working on a PLL and been using all the classic calculations for working out bandwidth, inlcuding the models presented in the analysis section of this web site. These all correlate and give the same results for bandwidth. However, silicon appears to give a bandwidth twice that predicted by the models and calculations. The only place I can think there may be a discrepency is in the Phase detector as everything else in the models is fairly simple. I am using a Phase Frequency detector that uses two edge triggered D-types with a delay in the feedback path for deadband compensation and I use the model of Kpd*deltatheta/2PI, where Kpd is the maximum magnitude of my charge pump output, though of course it can go negative as well as positive. This model I believe is correct for a phase detector, but is it valid for a Phase Frequency detector. If I simulate this block on its own purely with a phase offset but frequency locked then it does appear valid.
My peak current is 800uA so I use that figure in my calculations and model, but if I double it I get double the bandwidth, as you would expect, and the phase noise profile seen in simulation falls perfectly on top of our measured results.
Has anybody seen anything similar or can think of an explanation for the factor of two? One possible theory I have is the fact that the PFD responds to phase error in the normal way, but also responds to the frequency error (cumulative pahse error) and so the gain is effectively doubled, though I am very dubious about this theory.

Thanks in advance to anybody who can shed any light on this.
Andy