Paul
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Hi Sezi,
very interesting questions. As layout is more of a cookbook type of approach, with each cook having his own receipes, you shouldn't expect everybody to provide similar answers. My very personal point of view to your questions:
1. In modern technologies, via stacks should be quite well behaved (in some older ones they may not be allowed). As long as all transistors see the same stack, matching should not be affected.
2. Poly has higher series resistance than metal. Poly routing potentially lowers your transistor cut-off frequency, which is not shown in simulation, unless you do RC-extraction based post-layout simulation. In low-frequency designs, some poly routing may still be OK.
3. This depends on your system-level supply routing strategy. My general rule is to route for minimum series resistance in the supply connections.
4. Try to thinl about block assembly before drawing sub-block layouts. In this way, you know what shape you want each sub-block to have, including its terminal placements. Spending some time with this will save a lot of time in the assembly process.
5. I would say, try to separate noisy blocks from sensitive blocks. Depending on your charge pump design, it may be much noisier than the divider or the PFD...
I hope you will get other opinions to compare with.
Paul
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