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georgejor

Junior Member

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Posts: 15

simulate output impedance
Nov 10^th, 2005, 12:34am

Dear all,

I would like to simulate output impedance across a range of frequency. Could you help to check is the setting correct? thank you very much!

If there are any better method, please teach me!

Here is my setting:
++++++++++++++++++++++++++++++++++++++++++++++
** part of circuit with output node ("out")
M0 out node1 vdd vdd pch w=10 l=1
M1 node2 node3 out vdd pch w=10u l=1
**simulation setting
Iout out 0 dc=0 ac=1

.ac dec 100 10 1e9
Vdb(out)
++++++++++++++++++++++++++++++++++++++++++++++
Then I get the vdb(out) and I think it is 20*log(V/I) where I is 1 for all freq.
Therefore, it is output impedance (in db) across that range of freq.

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Visjnoe

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Re: simulate output impedance
Reply #1 - Nov 10^th, 2005, 8:01am

Hi,

Overall, your set-up seems fine: apply a 'test' current Iout
and watch the effect on the output voltage (or vice versa).

Since Zout = Vout/Iout and Iout (ac) == 1, the magnitude of the output voltage corresponds indeed with the output impedance of your circuit.

I find it strange however to assess it in dB (20*log(V/I)) which becomes 20*log(V) since I == 1 and this - of course- equals vdb(out).

Simply converting to decimal numbers would be my approach, but in the end, it's just another representation

Kind Regards

Peter

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flamingo

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Posts: 5

Re: simulate output impedance
Reply #2 - Nov 29^th, 2005, 8:56pm

Your simulation process based on basic definition of Zout, and also based on small-signal models of the schematic. So an very important thing is, you must care for keeping every component in your ckt stay in the exact operating point. Maybe you need some dc inputs and capacitors at the ouput which are used to seperate the dc access. Good Luck.
PS: AC plus Net commands can do this job.

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Croaker

Senior Member

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Posts: 235

Re: simulate output impedance
Reply #3 - Dec 8^th, 2005, 3:01pm

In general you have to ensure that your device has the correct DC bias. The output resistance given by AC analysis is dependent on the bias. In general, you add a DC source (if needed for biasing) and then perform an AC analysis to get output impedance.

For the circuit you presented, you are OK as long as the DC current from the test source is 0.

I also think it's odd to measure output impedance in dB. I'd just plot the output voltage, since Iac=1.

An alternate way to test that circuit would be to use a big cap at the output in series with your ac test voltage. The cap prevents the output from being ac-shorted to the test voltage. You could check the impedance looking into either FET by adding a big inductor to either drain. The inductor doesn't affect DC (sL=0) but forms a really big impedance. In other words (ron||zind) ~ ron.

Cheers,
Marc

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