hi all,

1. I get the 'segmentation violation' error when I instantiate this nand module

nand_gate #(.vlogic_high(1.2),.vlogic_low(0),.vtrans(0.54),.tdel(10p),.trise(20p),.tfall(2
0p)) Nand(a1,b1, out);


vlogic_high,vlogic_low ..etc are parameters declared in the module.

and I want to connect the 'in1' 'in2' and 'out' of the nand module to 'a1' 'b1' and 'out'

I am not sure as what the error signifies!

2. when instantiation , do the modules have to declared in "`include " I looked at various examples in this website, they were not declared. Does this assume the modules to be in the same directory.
I have tried the simualtion by including the module path using the `include ' /path/nand.va' ... doesnt seem to make a difference as far as the error message is concerned but Would like to know if this is necessary.

Thanks in advance!
S

Geoffry,

Thank you for replying!

I dont use spectre to run simulations. I use hsim which supports veriloga modules. so I write the testbench in spice and use '.hsimveriloga' statement to define the path to the veriloga module.

I have the nand gate written in veriloga and it seems to work fine when I run the simulations. I seem to have trouble only when I write a veriloga code to instantiate a module.

I have no idea as what the error means. dont know which directions to look to correct the error- the simulator, the code or the testbench. ?. Just posted it here to see if any one had this kind of problem before.


S