Verilog-A is a subset of Verilog-AMS.  Verilog-AMS has a language reference manual (LRM) available from http://www.eda.org/verilog-ams, and one of the appendices specifies what subsets of the LRM are part of Verilog-A.

The idea is that Verilog-A should consist only of things that can be simulated in an analog (spice-like) simulator.  AMS includes digital things and generally requires a second (digital) simulator running with the analog simulator.