Here's a little example, using a case statement. Note I'm also using
always @(S) which means that the code will get invoked any time S changes (positive or negative), and then a
case within. You could of course use
if within.
Code:`include "disciplines.vams"
module myres (a,b,S);
inout a,b;
input[1:0] S;
electrical a,b;
logic[1:0] S;
real rval;
always @(S)
case (S)
2'b00: rval=1.0K;
2'b01: rval=2.0K;
2'b10: rval=3.0K;
2'b11: rval=4.0K;
endcase
analog begin
V(a,b)<+I(a,b)*rval;
end
endmodule
This would then be compiled using:
Code:ncvlog -ams myres.vams
My testbench is as follows:
Code:`include "disciplines.vams"
module testit;
reg[1:0] S;
electrical agnd;
ground agnd;
electrical n1;
initial begin
S=2'b00;
#50 S=2'b01;
#50 S=2'b10;
#50 S=2'b11;
#50 $finish;
end
isource #(.dc(-1.0m)) I1(n1,agnd);
myres R1(n1,agnd,S);
endmodule
And to compile this:
Code:ncvlog -ams testit.vams
With an analog control file (very simple) of:
Code://
tran tran stop=400n
I can then elaborate and simulate with:
Code:ncelab testit
ncsim -gui -analogcontrol testit.scs testit
Attached is a png file (out of wavescan) showing the resulting waveforms (I'm plotting the voltage, as the resistor value changes). Note the model is pretty lousy, because it doesn't change the resistor value smoothly - it has an instantaneous switch (which is not a good thing), but this is just to illustrate the principle ;D