Hi,

Why don't you want to have a biasing network? I highly recommend you design a biasing network so that it will make your life easier. A biasing network will help track process, voltage and temperature variation and hence change the voltage bias accordingly. Also is the architecture differential or single-ended? If differential you need a CMFB network.

Hope this helps!

Hi Steven, the fact is that Vds will change as circuit voltages wiggle.  That's why there's an ICMR for an op-amp.  You basically just set Vgs to give you the right overdrive voltage AND you may have to use more gate voltage to make sure Vds is far enough away from Vds(sat).  Short-channel devices don't have an easy to define Vds(sat) so you basically have to decide where to bias Vds based on the desired amount of output resistance.

Does that answer your question?  I think you know what you are talking about but you just had some doubts about the design philosophy.

Hi Steven,

regarding your telescopic OTA, the source voltage of M1/M2 is defined by the input-common mode of the opamp and by the ratio Id1 / (W/L)1: in my opinion you should try to properly bias the M1/M2 since the CMFB loop will work fine only if the opamp's tail device is out of triode region (it seems to me that your CMFB is not working at all if the output common mode is 0.104V!!). You may want to enlarge your differential pair or raise the input common mode.

As a second matter, the voltage at the drain of M1/M2 is defined by the gate voltage of M3/M4 and by their size: again, you should enlarge M3/M4 since, in my opionion, a gate-to-source voltage equals to 2.45 is too high for M3/M4. The biasing of M3/M4 and M7/M8 is quite delicate for they should be properly saturated event when the opamp's output voltage is completely unbalanced (full swing condition): generally speaking, the telescopic architecture is suitable for medium-low output swing: if you require more swing (1.5V-2 V) you may design a replica-tail feedback loop (quite complicated for high-speed applications!) or change your topology toward a folded-cascode (more power-hungry!).

In order to find the appropriate biasing and size of M3/M4 you can also substitute MB5 with a voltage source and, once all is fixed, come back to MB5. That is a standard routine during the first design activities.  ;)

Bye,
Cri

Marc Murphy wrote on Jan 27^th, 2006, 7:40pm:



Hi Cri and Marc,

Thanks for both of you commenting on the circuit. As Marc said, I didn't size it correctly when I posted but tried to illustrate how to get around the Vsd7. I can size them to have open-loop gain at around 85dB but GBW is too small. Still I don't feel comfortable on something. Here are the parameters I used:

V+ and V- are at 1.5.

Vthn is 0.6, Vthp is -0.8. I tried to set |Vds(sat)| around 0.2. Actual Vds(sat) is about 0.3~0.4 (absolute value). Vds(Mb5) now is about 1.2V. It was really hard to set Vds(Mb5)=Vgs+Vds(sat) (I am happy to listen your tricks on doing this).

M10 is in trio mode though, Vds10=0.04 < Vds10(sat)=0.9. I don't if I still need to adjust it or not. The others are at Saturation.

Half branch current is 3.3mA, Id(Mb5) is 31uA. Maybe I should redraw the circuit to show the sizes. Before that, I want to ask these to Marc,

1. When you said make sure vbias MOS is 3x, what is the 3x compared to?

2. How do you do a vgs sweep? This is very useful since I didn't know how to set M3 and M4 efficiently before I posted the original post.

Regards,
Steven

Marc Murphy wrote on Jan 28^th, 2006, 3:43am:


Just a quick reply. Here I guess (really guessing) we had a misunderstanding of each other:

When you said "Vgs sweeping", you meant that connecting a *single* transistor and do a DC sweep to find correct Id and (W/L), right? (But hand calculation is quite close if I check with this sweeping setting up). If this is the case, I believe I asked a wrong question. I was thinking you were referring to Cri's comment, ie., fixing some voltage source then sweeping the other to find the appropriate Id and (W/L) while keeping the *whole* OTA topology. If this is not what meant, I need more comments from you.

Regards,
Steven

Let's say we want Vov=Vgs-Vth=0.1*Vdd=300 mV
So, Vgsn=Vthn+0.3=0.8 V
Vsgp=Vthp+0.3=1.1 V
sounds like Vds should be around 0.3 V for saturation
pick fT, which leads to your gm
do the vgs single tran sweep to find out what size gives you the right gm at your desired vgs (vds is set to around or more than vds(sat))

now you know the sizes for all NMOS and PMOS in your circuit.  M1, M2, M3, M4 are going to be the same size.  All PMOS are the same size.  I think the thing that may have messed you up is that the PMOS were not sized right relative to the NMOS.  The KEY to making the rest of the circuit work is the proper sizing of MOSFETs and now you have almost all of the sized to sink the right current at the chosen bias voltages.

Each PMOS branch will have roughly the same current when in saturation.  You size M10 to take all the current, so it is 3x bigger than the other NMOS.  You make Mb5 smaller to raise its voltage to at least vgs+vds, to keep M3 & M1 happy.


steven wrote on Jan 27^th, 2006, 9:01pm:

Hello Marc,

I tried the sizing method you suggested. Here are some followups and thoughts.

1. you are right that the ratio between PMOS and NMOS can easily mess sizes obtained from single tran sweep results. In other words, Vsd7 would be still too big even though individual tran has been sized correctly in single tran sweep. So when connecting PMOS and NMOS, the sizes have to be redone again. I hope I didn't do anything different than what you said regarding this.

Some sizes I adopted at single tras sweep are: NMOS (W/L)=200/0.5 leads to gm=14.5mS, PMOS (W/L)=500/1 leads to gm=12mS. Put them in the circuit place, Vsd7 is around 1.6 (after some minor tweaking), still too big.

2. I think using fT to pick gm should be the same as using Id, (W/L), and Vgs method in single tran connection. Besides, you may have other ways to choose fT, which is a function of parasitic cap also the transistor size and gm.

3. I think since Mb5 is simply to generate bias voltage for M1~M4, it may not require to have the same branch current as M1 and M2 branch. Of course, assuming the three branch have the same current can greatly siimplify the design.

Regards,
Steven