Firstly, sorry for my poor english...

I am having some troubles in my project. I am designig a double balanced mixer CMOS which uses a PMOS as a active load ( current source, exactly ). The RF and LO ports are perfectly matched, but the IF port no. While I got an excellent IIP3 point ( +14.2 dBm ) and reasonable Noise Figure ( NF = 14.4 dB ),  my circuit´s conversion gain is low ( CG = -7.7 dB ).  I use a current of, approximately 12 [mA] and the transistors´dimensions are : W_RF=200 [um] and L_RF=L_min ( 0.25 [um] ), W_LO=300 [um] and L_LO=L_min and, the active loads, W_AL=650 [um] and L_AL=0.35 [um]. I got these values to estipulate DC voltages on especific nodes. For example, the DC voltage at IF node is 2.4 [V] ( VDD = 3.3 [V] and TSMC 0.25 [um] process ). Please, can you help me ? I need a better CG... I am sending the schematic attached.

Thank you very much.

Thank you for your answer, sonny.

What kind of CMFB ? I dont wanna to use resistors in my design. This is a project constraint. And what about the Conversion Gain ( CG ) ? How can I make it better ?

One more time,

Thank you very much.

Fabricio

fab_jor wrote on Feb 25^th, 2006, 1:16pm:


About CMFB , detect mixer output DC voltage by LPF, compare the voltage and specific voltage by comparator, control the PMOS current using comparator output to set the mixer output DC voltage to specific one. I guess low PMOS output impedance make conversion gain low, so I recommend longer PMOS L ( about 1um or 2um).

Thank you for your reply, Sonny.

But I cant understand about the CMFB's circuit. What kind of circuit I must use ? Can you send me a topology/schematic ? I already tried another active load ( a current mirror and I got a better conversion gain ), but never better than 0 [dB] and the output impedance was not equals between the outputs. The IIP3 is great ( about +13 [dBm] ) and I utilize a 12.5 [mA] as the bias current. I think that, if I lower that current, I will get a better conversion gain. What do you think ? I dont understand because my circuit's conversion gain is too low, if I am using active loads ? Do you know why ?

Best regards.

Fabricio

Hi,

Did you try increasing the current? I think increasing the current in the gain stage will help improve the CG as it will improve the gm of the transistor. May be you should try with 20mA.

Also you could use just one degeneration element between the sources of the transistors forming the gain stage (place it across the two sources), and use two current sink transistors at the sources instead of one common one. This will reduce the voltage drop across the resistors.

Regards,

Hi sonny and RFenthusiast


RFenthusiast:

Changing the current ( 3 [mA] and 20 [mA] ) dont make the CG better... I got a good IIP3...

sonny:

The PMOS's output resistance ( Rds or 1/Gds ) is higher than 10k. The RF stage's Gm is about 55 m.

So, I dont know what is wrong with my design. I simply cant get a good CG !!!

Any sugestions ?

Regards.