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wjx197733

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how to analyse this circuit?
Feb 28^th, 2006, 5:05pm

Hi, all: the file in the attachment is a OPA and this circuit puzzles me.

1.why we must use the Q6 and Q7 which act as a class B push-pull output stage? and why Q6 and Q7 can act as a class B push-pull output stage?

2.the dc biasing is designed so that Q8 and Q9 have equal-value small gate-to-source dc bias. This maximizes the linear Vout range. I do not know why.

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circuit.JPG

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Paul

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Switzerland

Re: how to analyse this circuit?
Reply #1 - Mar 1^st, 2006, 3:57am

Hi,

1) I wouldn't say Q6 and Q7 form a push-pull stage. As both are PMOS devices, they form a source follower stage (Q7 is simply a current source). The goal basically is to replace the PMOS current source inthe output branch of a classical Miller-OTA by an active device, which improves the dynamic behavior.

2) For Q8 (NMOS), Vgs8=Va. For Q9 (PMOS), Vgs9=Va-Vgs6-Vdd (provided you consider PMOS Vgs values as negative). Can you provide us with the reference to this publication/book?

Paul

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vivkr Community Fellow Offline Posts: 780	Re: how to analyse this circuit? Reply #2 - Mar 1^st, 2006, 7:54am Hi Paul, I agree with you. This looks like a way of improving dynamic performance. As for the book, my guess would be that this is either from Gregorian/Temes (SC filter book) or Gregorian's book on opamps. The drawing style is pretty distinctive. Regards Vivek
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chase.ng

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penang/malaysia

Re: how to analyse this circuit?
Reply #3 - Mar 13^th, 2006, 9:36am

Hi,

I think the output is class AB. Since when idle, both Q8 Q9 will conduct some current. My opinion is that the OTA is designed to have widest output swing/current possible, therefore Q8 is NMOS n Q9 is PMOS. The differential pair have no prob driving Q8 but Q9 needs a level shifter which I think is formed by Q7 and Q6. Please correct me if I am wrong.

Regards,
Chase

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Chase

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Raul

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Posts: 37
San Jose, CA.

Re: how to analyse this circuit?
Reply #4 - Mar 19^th, 2006, 8:41pm

I think this circuit has a pretty bad problem because the current in the output stage is dependent upon the power supply. The voltage at the gate of Q6 is fixed to VGS,Q8 and the source will track the supply via the VGS,Q9.
I wouldn't use this circuit if I where you. There are way better class AB biasing circuits out there, if you want I can sketch one and post it.
In this circuit your phase margin would be at a minimum for the lowest supply voltage and this would in turn affect your settling time, etc... Not a good characteristic for an amplifier circuit.

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regards, Raul Perez

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