Im trying to learn verilog and Im having some problems. Mainly I dont really understand the difference between the different types of synsthesis, Behavioral vs RTL vs Gate level.
From my understanding Gate Level synthesis is just using the logic gate commands, e.g. AND OR XOR NOR, etc., so for example this would be a 2x1 multiplexer written in gate level:
Code: module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;
wire a, b;
and(a, sel, in1);
and(b, ~sel, in2);
or(out, a, b);
endmodule
RTL and behavioral really dont make sense to me. From what Ive read behavioral synthesis is just creation using control flow statements (if, then, else, for, while, etc.), much like c/c++. So that a behavioral 2x1 mux would be something like:
Code: module muxy(in1, in2, sel, out);
input in1;
input in2;
input sel;
output out;
if (sel==0 & in1=0 & in2=1)
assign out=1;
else if (sel=0 & in1=0 & in2=0)
assign out=0;
else blah blah blah
endmodule
Is that correct for behavioral?
As for Register Transfer Level, Im pretty lost, I dont see any other sort of coding style it could be.
Finally, Im having trouble finding good learning sources online, can anyone link me some good tutorials, more importantly example code for simple problems like 2x1 muxes?