Hi,
I'm not 100% sure, but this jitter requirement seems very tough to realize in 130nm CMOS... Don't forget that each driver stage you add at the clock output also adds jitter, so your oscillator should even be better than your spec. For illustration purpose, 2ps
RMS is current state-of-the-art for high-performance oscilloscope time bases, which usually use SiGe components
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In any case, don't forget to put the oscillator on a separate regulated power supply to minimize additional noise due to limited PSRR. Possibly a single-ended topology has less device noise sources and may improve the overall noise, but of course it has other issues like substrate and supply sensitivity...
May I ask why you are limited to ring oscillator topologies if the jitter specs are so stringent?
Good luck
Paul