packiaraj
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Hi Forum, I am verifying a Recirculating Pipelined ADC design. It is 10 Bit, 1MSPS design. Positive Input INP can swing from 2V to 1V and Negative Input INN=1V. Common Mode Voltage for OPAMP is 1.5V. It is 1.5Bit/Stage design. We have 2 such stages. The output residue of second stage is fedback as input to the first stage. For the first clock cycle SHA output will be sampled by first stage. For the rest of 9 clock cycles the first stage will sample the residue fedback by the second stage. The second stage will always sample the residue output of first stage.
In this design, we have 2 coarse comparators (Fully Differential Dynamic) in MDAC stage. The Interstage gain is 2. The SHA output swing is from 1V to 2Volt with CM=1.5V. I see from the design the whole input range is divided by 8. i.e., (2-1) /8=0.125V. The reference voltages applied to comparator are 1+3/8(0.125)=1.375 and 1+5/8(0.125)=1.625. . When the input is in the range [1:1.325) the thermometer code output of comparators is 00. For [1.325:1.625], it is 01 and for (1.625:2], it is 11. When output is 00 , 1V will be selected for subtraction, when 01, 1.5Vwill be selected, when 11, 2V will be selected for subtraction in generating the residue. But, When I simulated the top level design I saw too much of missing codes.
But to my understanding the reference voltages should be -Vref/4 and +Vref/4. In this case (2-1)/4=0.25., 1.25V and 1.75V instead of 1.375 and 1.625. What could be the exact values comparator reference voltages for this design? Ur input is invaluable........ Please help.
Thanks, Packiaraj.V.
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