Hi!

I am designing charge pump in PLL.

But, I don't know problem for designing charge pump.

I want to design charge pump that have a value of voltage limitation at output.

This is a source code.

module CP4 (vsrc, vref, siginc, sigdec, vout );

input   siginc, sigdec;
inout   vsrc, vref, vout;
electrical      vsrc, vref, siginc, sigdec, vout;
parameter       real iamp = 1m from [0:inf);
parameter       real vtrans = 1.25 from [0:inf);
parameter       integer cpmax = 5 from [0:inf);

integer inc_high;
integer dec_high;
integer selelec;        // selection flag of electrical(1:potential, 0:flow)

analog begin
//        @(initial_step) begin
//        V(vout, vref) <+ V(vsrc, vref)/2;
//        end

       inc_high = V(siginc) > vtrans;
       dec_high = V(sigdec) > vtrans;

       if (V(vout, vref) > cpmax )
               selelec = 1;
       else
               selelec = 0;

       @(cross(V(siginc) - vtrans, 1)) begin
               if (selelec)
                       V(vout, vref) <+ 2.5;
               else
                       I(vsrc, vout) <+ iamp;
       end

       @(cross(V(sigdec) - vtrans, 1)) begin
               if (selelec)
                       V(vout, vref) <+ 2.5;
               else
                       I(vref, vout) <+ -iamp;
       end
end
endmodule

This code is compiled but i can't simulated it for segentation fault.

Please, Help Me!!!! T T

Thanks for your advice.

I could have referenced charge pump cell in ahdlLib library.
But I don't know solution to this cell, too.
This cell use a analog function, thus only control state of current.
I want to know how to limit output voltage in this cell.
this is charge pump code in ahdlLib.
I modified to select branch in this code.

I(vsrc, vout)<+ iout_val; // Original Code

if (V(vout) < 2.5)
I(vsrc, vout) <+ iout_val;
else
V(vout) <+2.5; // Modified code

But i still can't simulate it for convergence.
I thought that modifed code generates abrupt chage.
But I can't change abstol in PLL.

I appreciate your help. Thanks.


//--------------------
// charge_pump
//
// -  Charge pump
//
// vout:            output terminal from which charge pumped/sucked [V,A]
// vsrc:            source terminal from which charge sourced/sunk  [V,A]
// siginc,sigdec:      Logic signal that control charge pump operation [V,A]
//
// INSTANCE parameters
//    iamp        = charging current magnitude [A]
//    vtrans      = voltages above this at input are considered high [V]

//
// MODEL parameters
//    {none}
//
// This model can source of sink a fixed current, 'iamp'. Its mode
// depends on the values of 'siginc' and 'sigdec';
//    
//    When 'siginc' > 'vtrans', 'iamp' Amps are pumped from the output.
//    When 'sigdec' > 'vtrans', 'iamp' Amps are sucked into the output.
//    When both 'siginc' & 'sigdec' in same state - no current sucked/pumped.
//

module charge_pump(siginc, sigdec, vout, vsrc);
input siginc, sigdec;
inout vout, vsrc;
electrical siginc, sigdec, vout, vsrc;
parameter real iamp=0.5m from [0:inf);
parameter real vtrans = 2.5;

  real iout_val;

  //
  // Current multiplier - returns direction that charge should be pumped
  //
  analog function real i_mult;
  input inc;
  input dec;
  input vtrans;
  real inc;
  real dec;
  real vtrans;

     integer inc_high;
     integer dec_high;
 
  begin
     inc_high = inc > vtrans;
     dec_high = dec > vtrans;
     i_mult = 0.0;
     if (inc_high == dec_high) begin
        i_mult = 0.0;
     end else if (inc_high) begin
        i_mult = 1.0;
     end else if (dec_high) begin
        i_mult = -1.0;
     end
  end  
  endfunction

  analog begin
     @ ( initial_step ) begin
      iout_val = iamp*i_mult(V(siginc), V(sigdec), vtrans);
     end

     @ (cross(V(siginc) - vtrans, 0)) begin
        iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
     end
     @ (cross(V(sigdec) - vtrans, 0)) begin
        iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans);
     end

     I(vsrc, vout) <+ iout_val;
  end
endmodule

jjun2003 wrote on Apr 5^th, 2006, 8:48pm:


Are you sure you want the cross to detect transitions in both directions?  I would expect that "siginc" would go high to say "start charging up" and then "siginc" could go low but the pump would keep putting out positive current until "sigdec" triggers.  That is, I would make the second argument to cross a +1 to only detect positive-going transitions.

Thanks for your advice.

BUT I can't work it for bus error.

If i add your codes before (I(vsr,vout)<+transition...) I can run simulation.
(BUT vout_cl is LOW(=), unconditionally)
May you give me a full code?

Following that modified code.

parameter integer clamp=1 from [0:1];
...
//      I(vsrc, vout) <+ transition(iout_val, tdel, trise, tfall);   // This causes bus error!!!
     if (V(vout) > V(vsrc)) begin
                 I(vout) <+ clamp*1e6*(V(vout)-V(vsrc));
     end else if (V(vout) < 0) begin
           I(vout) <+ clamp*1e6*V(vout);
     end
     I(vsrc, vout) <+ transition(iout_val, tdel, trise, tfall);

I always appreciate your help. ^^