jjun2003
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Thanks for your advice.
I could have referenced charge pump cell in ahdlLib library. But I don't know solution to this cell, too. This cell use a analog function, thus only control state of current. I want to know how to limit output voltage in this cell. this is charge pump code in ahdlLib. I modified to select branch in this code.
I(vsrc, vout)<+ iout_val; // Original Code
if (V(vout) < 2.5) I(vsrc, vout) <+ iout_val; else V(vout) <+2.5; // Modified code
But i still can't simulate it for convergence. I thought that modifed code generates abrupt chage. But I can't change abstol in PLL.
I appreciate your help. Thanks.
//-------------------- // charge_pump // // - Charge pump // // vout: output terminal from which charge pumped/sucked [V,A] // vsrc: source terminal from which charge sourced/sunk [V,A] // siginc,sigdec: Logic signal that control charge pump operation [V,A] // // INSTANCE parameters // iamp = charging current magnitude [A] // vtrans = voltages above this at input are considered high [V]
// // MODEL parameters // {none} // // This model can source of sink a fixed current, 'iamp'. Its mode // depends on the values of 'siginc' and 'sigdec'; // // When 'siginc' > 'vtrans', 'iamp' Amps are pumped from the output. // When 'sigdec' > 'vtrans', 'iamp' Amps are sucked into the output. // When both 'siginc' & 'sigdec' in same state - no current sucked/pumped. //
module charge_pump(siginc, sigdec, vout, vsrc); input siginc, sigdec; inout vout, vsrc; electrical siginc, sigdec, vout, vsrc; parameter real iamp=0.5m from [0:inf); parameter real vtrans = 2.5;
real iout_val;
// // Current multiplier - returns direction that charge should be pumped // analog function real i_mult; input inc; input dec; input vtrans; real inc; real dec; real vtrans;
integer inc_high; integer dec_high; begin inc_high = inc > vtrans; dec_high = dec > vtrans; i_mult = 0.0; if (inc_high == dec_high) begin i_mult = 0.0; end else if (inc_high) begin i_mult = 1.0; end else if (dec_high) begin i_mult = -1.0; end end endfunction
analog begin @ ( initial_step ) begin iout_val = iamp*i_mult(V(siginc), V(sigdec), vtrans); end
@ (cross(V(siginc) - vtrans, 0)) begin iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans); end @ (cross(V(sigdec) - vtrans, 0)) begin iout_val = iamp*i_mult(V(siginc),V(sigdec),vtrans); end
I(vsrc, vout) <+ iout_val; end endmodule
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