Hi,

The restriction on V(G,S) and V(G,D) is quite a well known one and easy to understand for me
as these are the voltages across the gate oxide. However, I have often heard people mention to me
that the V(G,B) should also be kept within the same limits. This is not quite clear to me.

It is also not mentioned in any papers on bootstrapped switch design where it ought to cause
problems if it really is an issue.

As far as I can make out, the B (bulk) node is shielded from the G by the presence of the channel in
between. Hence, if one were to increase V(G) beyond a certain point,

V(G) > V(S) + Vth(V(S)), including body effect, then the channel would be formed
within a matter of a few device transit times, thus shielding the bulk. As the time taken for
the channel to form would be much less than the risetime of the signal driving the gate ON (coming
form another on-chip device, and hence limited by RC), this can be neglected.

Why then ought we to worry about V(G,B)? I think the real V(G,B) is just the value
I mentioned above and would be ~ V(S),max + Vth (V(S),max).

Regards
Vivek