I came across a differential FF ( had data /datab and out/outb)which has a -ve setup time and +ve hold time. This has me throughly confused. Supposed the setup time is -10ps and hod time is 30ps ,and clock starts at 0s-does this mean in the time from the 0 to 30ps if there is a transition on the data , the FF fails?.. How would you distingusih between setup violation and a hold violation?

Moreover if the data transistion is from 0 to 1 or 1 to 0 how would this affect the setup/hold time?

Would appreciate if anyone throws light on this....?

Hi,

I think -ve setup time occurs in pulse triggered Latches (FF) , this means that your differential circuit is pulse controlled.
In this case the FF is transparent in the period of the pulse, and for the FF to detect the data, the data should be ready on the input either before the first edge of the pulse or after it by maximum 10ps as in your example, after the transition it should be kept at the new level at least 30ps.

This means that as you say any data transition after 10ps will cause the FF to fail, it is not because of the setup time violatioin but because of the hold time which will be violated.

about the high to low or low to high, I think yes , it depends on the FF design because the setup time in latches  (if we agree to call it setup time in case of latches) is dependent on the direction of the signal transition. This conclusion I had from past simulations. Inorder to discuss it I think we should discuss the design of the Latch you are using.

Best regards,

aamar