Hi Dave,

It seems from the description "... dump the **periods** to a text file and find the variance in Matlab..." that the jitter that you are referring to is period-to-period jitter. For a same VCO, the measured period-to-period (or cycle-to-cycle) jitter is normally much smaller than its long term jitter, which means that the actually long-term jitter of your PLL can be much larger than the value you assumed. Therefore, I suspect that the jitter you used to stress you PLL is too large.

I would suggest you to lock you PLL to a jitter-free reference clock source, trigger you waveform viewer or MATLAB routine to this reference clock, and plot the jitter histogram of the PLL output signal. You will probably see larger jitter than you have assumed. If it is so, your requirement on design is too high. Just try to relax the jitter to the appropriate amount.

By the way, I think it make more sense to jitterize your input data rather than the VCO. This is more realisitic, since a LC-VCO that you will most probably use in your 5Gbps high performance design will definitively have an RMS jitter less than 1ps (asuming the jitter is calculated by integrating the free running VCO phase noise from 50kHz to 80MHz). Furthermore, you can also test the jitter transfer function and jitter tolerance of the CDR with this setup. To do this, you need to trigger your PRBS generator with a jittered clock source.

Regards,

Jiawen Hu
Analog Design